RE=0, RIE=0, FEIE=0, TIE=0, TXINV=0, NEIE=0, TCIE=0, ILIE=0, RWU=0, MA1IE=0, DOZEEN=0, WAKE=0, ORIE=0, IDLECFG=000, TXDIR=0, LOOPS=0, TE=0, PEIE=0, MA2IE=0, SBK=0, RSRC=0, M=0, ILT=0, PE=0, PT=0
LPUART Control Register
| PT | Parity Type 0 (0): Even parity. 1 (1): Odd parity. |
| PE | Parity Enable 0 (0): No hardware parity generation or checking. 1 (1): Parity enabled. |
| ILT | Idle Line Type Select 0 (0): Idle character bit count starts after start bit. 1 (1): Idle character bit count starts after stop bit. |
| WAKE | Receiver Wakeup Method Select 0 (0): Configures RWU for idle-line wakeup. 1 (1): Configures RWU with address-mark wakeup. |
| M | 9-Bit or 8-Bit Mode Select 0 (0): Receiver and transmitter use 8-bit data characters. 1 (1): Receiver and transmitter use 9-bit data characters. |
| RSRC | Receiver Source Select 0 (0): Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the LPUART_RX pin. 1 (1): Single-wire LPUART mode where the LPUART_TX pin is connected to the transmitter output and receiver input. |
| DOZEEN | Doze Enable 0 (0): LPUART is enabled in Doze mode. 1 (1): LPUART is disabled in Doze mode. |
| LOOPS | Loop Mode Select 0 (0): Normal operation - LPUART_RX and LPUART_TX use separate pins. 1 (1): Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). |
| IDLECFG | Idle Configuration 0 (000): 1 idle character 1 (001): 2 idle characters 2 (010): 4 idle characters 3 (011): 8 idle characters 4 (100): 16 idle characters 5 (101): 32 idle characters 6 (110): 64 idle characters 7 (111): 128 idle characters |
| MA2IE | Match 2 Interrupt Enable 0 (0): MA2F interrupt disabled 1 (1): MA2F interrupt enabled |
| MA1IE | Match 1 Interrupt Enable 0 (0): MA1F interrupt disabled 1 (1): MA1F interrupt enabled |
| SBK | Send Break 0 (0): Normal transmitter operation. 1 (1): Queue break character(s) to be sent. |
| RWU | Receiver Wakeup Control 0 (0): Normal receiver operation. 1 (1): LPUART receiver in standby waiting for wakeup condition. |
| RE | Receiver Enable 0 (0): Receiver disabled. 1 (1): Receiver enabled. |
| TE | Transmitter Enable 0 (0): Transmitter disabled. 1 (1): Transmitter enabled. |
| ILIE | Idle Line Interrupt Enable 0 (0): Hardware interrupts from IDLE disabled; use polling. 1 (1): Hardware interrupt requested when IDLE flag is 1. |
| RIE | Receiver Interrupt Enable 0 (0): Hardware interrupts from RDRF disabled; use polling. 1 (1): Hardware interrupt requested when RDRF flag is 1. |
| TCIE | Transmission Complete Interrupt Enable for 0 (0): Hardware interrupts from TC disabled; use polling. 1 (1): Hardware interrupt requested when TC flag is 1. |
| TIE | Transmit Interrupt Enable 0 (0): Hardware interrupts from TDRE disabled; use polling. 1 (1): Hardware interrupt requested when TDRE flag is 1. |
| PEIE | Parity Error Interrupt Enable 0 (0): PF interrupts disabled; use polling). 1 (1): Hardware interrupt requested when PF is set. |
| FEIE | Framing Error Interrupt Enable 0 (0): FE interrupts disabled; use polling. 1 (1): Hardware interrupt requested when FE is set. |
| NEIE | Noise Error Interrupt Enable 0 (0): NF interrupts disabled; use polling. 1 (1): Hardware interrupt requested when NF is set. |
| ORIE | Overrun Interrupt Enable 0 (0): OR interrupts disabled; use polling. 1 (1): Hardware interrupt requested when OR is set. |
| TXINV | Transmit Data Inversion 0 (0): Transmit data not inverted. 1 (1): Transmit data inverted. |
| TXDIR | LPUART_TX Pin Direction in Single-Wire Mode 0 (0): LPUART_TX pin is an input in single-wire mode. 1 (1): LPUART_TX pin is an output in single-wire mode. |
| R9T8 | Receive Bit 9 / Transmit Bit 8 |
| R8T9 | Receive Bit 8 / Transmit Bit 9 |